View LT1933_4620029.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3510 1 3510fe typical application features applications description monolithic dual tracking 2a step-down switching regulator the lt ? 3510 is a dual current mode pwm step-down dc/dc converter with two internal 2.5a switches. inde- pendent input voltage, feedback, soft-start and power good pins for each channel simplify complex power supply tracking/sequencing requirements. both converters are synchronized to either a common external clock input or a resistor programmable ? xed 250khz to 1.5mhz internal oscillator. at all frequencies, a 180 phase relationship between channels is maintained, reducing voltage ripple and component size. programmable frequency allows for optimization between ef? ciency and external component size. minimum input-to-output voltage ratios are improved by allowing the switch to stay on through multiple clock cycles, only switching off when the boost capacitor needs recharging, resulting in ~95% maximum duty cycle. each output can be independently disabled using its own soft-start pin, or by using the shdn pin the entire part can be placed in a low quiescent current shutdown mode. the lt3510 is available in a 20-lead tssop package with exposed leadframe for low thermal resistance. n dsp power supplies n disc drives n dsl/cable modems n wall transformer regulation n distributed power regulation n pci cards n wide input range: 3.1v to 25v n two switching regulators with 2a output capability n independent supply to each regulator n adjustable/synchronizable fixed frequency operation from 250khz to 1.5mhz n antiphase switching n outputs can be paralleled n independent, sequential, ratiometric or absolute tracking between outputs n independent soft-start and power good pins n enhanced short-circuit protection n low dropout: 95% maximum duty cycle n low shutdown current: <10a n 20-lead tssop package with exposed leadframe 3.3v and 1.8v dual 2a step-down converter with output tracking ef? ciency shdn 4.7f 47f 100f 24.9k 61.9k 8.06k 470pf 10pf 47pf 40.2k 4.7h 3.3h v out1 3.3v 2a v out2 1.8v 2a v in 12v 0.47f b360a b360a 0.47f pmeg4005 pmeg4005 v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 r t /sync bst2 sw2 ind2 v out2 pg2 fb2 v c2 ss/track2 10k 8.06k 3510 ta01a 0.1f 470pf 40.2k load current (a) 0 0 efficiency (%) 20 40 60 0.5 1 1.5 3510 ta01b 80 100 10 30 50 70 90 2 v out = 5v v out = 3.3v v out = 2.5v v out = 1.8v v in = 12v i out2 = 0a frequency = 500khz l , lt, ltc, ltm, linear technology, burst mode and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
lt3510 2 3510fe electrical characteristics absolute maximum ratings v in1/2 , shdn, pg1/2 ...................................... 25v/C0.3v sw1/2 ....................................................................v in1/2 bst1/2 ........................................................... 35v/C0.3v bst1/2 pins above sw1/2 ........................................25v ind1/2 .....................................................................4a v out1/2 ........................................................ v in1/2 /C0.3v fb1/2, ss1/2, r t /sync ............................................5.5v v c1/2 ......................................................................1ma operating junction temperature range lt3510efe (notes 2, 8) ..................... C40c to 125c lt3510ife (notes 2, 8) ...................... C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t j = 25c. v vin1/2 = 15v, v bst1/2 = open, v rt/sync = 2v, v vout1/2 = open, unless otherwise speci? ed. parameter conditions min typ max units shdn threshold v out1/2 = 0v, r t /sync = 133k l 1.23 1.28 1.37 v shdn input current v shdn = 1.375v v shdn = 1.225v 7 2 10 3 13 5 a a minimum input voltage ch 1 (note 3) v fb1/2 = 0v, v vout1/2 = 0v, v ind1/2 = 0v, r t /sync = 133k 2.8 3 v minimum input voltage ch 2 v fb1/2 = 0v, v vout1/2 = 0v, v ind1/2 = 0v 2.8 3 v supply shutdown current ch 1 v shdn = 0v l 930 a supply shutdown current ch 2 v shdn = 0v 0 5 a supply quiescent current ch 1 v fb1/2 = 0.9v 3.5 5 ma supply quiescent current ch 2 v fb1/2 = 0.9v 200 500 a feedback voltage ch 1/2 v vc1/2 = 1v l 0.784 0.8 0.816 v pin configuration fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 v in1 sw1 ind1 v out1 pg1 pg2 v out2 ind2 sw2 v in2 bst1 ss/track1 v c1 fb1 r t /sync shdn fb2 v c2 ss/track2 bst2 21 t jmax = 125c, ja = 45c/w, jc(pad) = 10c/w exposed pad (pin 21) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3510efe#pbf lt3510efe#trpbf lt3510fe 20-lead tssop C40c to 125c lt3510ife#pbf lt3510ife#trpbf lt3510fe 20-lead tssop C40c to 125c lead based finish tape and reel part marking* package description temperature range lt3510efe lt3510efe#tr lt3510fe 20-lead tssop C40c to 125c lt3510ife lt3510ife#tr lt3510fe 20-lead tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
lt3510 3 3510fe electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. parameter conditions min typ max units feedback voltage line regulation v vin1/2 = 3v to 25v l C1 0 1 % feedback voltage offset ch 1 to ch 2 v vc1/2 = 1v l C16 0 16 mv feedback bias current ch 1/ch 2 v fb1/2 = 0.8v, v vc1/2 = 1v l C200 75 200 na error ampli? er g m ch 1/ch 2 v vc1/2 = 1v, i vc1/2 = 5a l 150 275 450 mho error ampli? er gain ch 1/ch 2 1000 v/v error ampli? er to switch gain ch 1/ch 2 2.2 a/v error ampli? er source current ch 1/ch 2 v fb1/2 = 0.6v, v vc1/2 = 1v 10 15 25 a error ampli? er sink current ch 1/ch 2 v fb1/2 = 1v, v vc1/2 = 1v 15 20 30 a error ampli? er high clamp ch 1/ch 2 v fb1/2 = 0.7v 1.75 2.0 2.25 v error ampli? er switching threshold ch 1/ch 2 v out1/2 = 5v, r t /sync = 133k 0.5 0.7 1.0 v soft-start source current ch 1/ch 2 v fb1/2 = 0.6v, v ss1/2 = 0.4v l 2 3 4.2 a soft-start v oh ch 1/ch 2 v fb1/2 = 0.9v 1.9 2 2.4 v soft-start sink current ch 1/ch 2 v fb1/2 = 0.6v, v ss1/2 = 1v 200 600 1000 a soft-start v ol ch 1/ch 2 v fb1/2 = 0v 50 80 125 mv soft-start to feedback offset ch 1/ch 2 v vc1/2 = 1v, v ss1/2 = 0.4v l C16 0 16 mv soft-start sink current ch 1/ch 2 por v ss1/2 = 0.4v (note 4), v vc = 1v 0.5 1.5 2 ma soft-start por threshold ch 1/ch 2 v fb1/2 = 0v (note 4) 55 80 105 mv soft-start switching threshold ch 1/ch 2 v fb1/2 = 0v 30 50 70 mv power good leakage ch 1/ch 2 v fb1/2 = 0.9v, v pg1/2 = 25v, v vin1/2 = 25v, v out = 5v 0 1 a power good threshold ch 1/ch 2 v fb1/2 rising, pg1/2 = 20k to 5v l 87 90 93 % power good hysteresis ch 1/ch 2 v fb1/2 falling, pg1/2 = 20k to 5v 20 30 50 mv power good sink current ch 1/ch 2 v fb1/2 = 0.65v, v pg1/2 = 0.4v 400 800 1200 a power good shutdown sink current ch 1/ch 2 v vin1/2 = 2v, v fb1/2 = 0v, v pg1/2 = 0.4v 10 50 100 a r t /sync reference voltage v fb1/2 = 0.9v, i rt/sync = C40a 0.93 0.975 1 v switching frequency r t /sync = 133k, v fb1/2 = 0.6v, v bst1/2 = v sw + 3v r t /sync = 15.4k, v fb1/2 = 0.6v, v bst1/2 = v sw + 3v 200 1.2 250 1.5 300 1.8 khz mhz switching phase angle ch a to ch b r t /sync = 133k, v fb1/2 = 0.6v, v bst1/2 = v sw + 3v 120 180 210 deg minimum boost for 100% duty cycle ch 1/ch 2 v fb1/2 = 0.7v, i rt/sync = C35a (note 5), v out = 0v 1.7 2 v sync frequency range v bst1/2 = v sw + 3v 250 1500 khz sync switching phase angle ch a to ch b sync = 250khz, v bst1/2 = v sw + 3v 120 180 210 deg ind + v out current ch 1/ch 2 v vout1/2 = 0v, v fb1/2 = 0.9v v vout1/2 = 5v 40 70 0 100 1 a a ind to v out maximum current ch 1/ch 2 v vout1/2 = 0.5v (note 6), v fb1/2 = 0.7v, v bst1/2 = 20v v vout1/2 = 5v (note 6), r t /sync = 133k, v bst1/2 = 20v 2.25 2.5 2.8 2.8 4 4 a a switch leakage current ch 1/ch 2 v sw1/2 = 0v, v vin1/2 = 25v l 050 a switch saturation voltage ch 1/ch 2 i sw1/2 = 2a, v bst1/2 = 20v, v fb1/2 = 0.7v l 250 400 mv boost current ch 1/ch 2 i sw1/2 = 2a, v bst1/2 = 20v, v fb1/2 = 0.7v 25 50 100 ma minimum boost voltage ch 1/ch 2 i sw1/2 = 2a, v bst1/2 = 20v, v fb1/2 = 0.7v (note 7) 1.4 2.5 v note 2: the lt3510efe is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t j = 25c. v vin1/2 = 15v, v bst1/2 = open, v rt/sync = 2v, v vout1/2 = open, unless otherwise speci? ed.
lt3510 4 3510fe typical performance characteristics electrical characteristics lt3510ife is guaranteed and tested over the full C40c to 125c operating junction temperature range. note 3: minimum input voltage is de? ned as the voltage where internal bias lines are regulated so that the reference voltage and oscillator remain constant. actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. see applications information. note 4: an internal power-on reset (por) latch is set on the positive transition of the shdn pin through its threshold. the output of the latch activates current sources on each ss pin which typically sink 1.5ma, discharging the ss capacitor. the latch is reset when both ss pins are driven below the soft-start por threshold or the shdn pin is taken below its threshold. note 5: to enhance dropout operation, the output switch will be turned off for the minimum off time only when the voltage across the boost capacitor drops below the minimum boost for 100% duty cycle threshold. note 6: the ind to v out maximum current is de? ned as the value of current ? owing from the ind pin to the v out pin which resets the switch latch when the v c pin is at its high clamp. note 7: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. feedback voltage vs temperature r t /sync voltage vs temperature shutdown threshold and minimum input voltage vs temperature shutdown quiescent current vs temperature soft-start source current vs temperature temperature (c) C50 voltage (v) 0.806 0.811 0.816 25 75 3510 g02 0.801 0.796 C25 0 50 100 125 0.791 0.786 temperature (c) C50 C25 0.95 voltage (v) 0.99 1.05 0 50 75 3510 g03 0.97 1.03 1.01 25 100 125 temperature (c) C50 voltage (v) 2.0 2.5 3.0 25 75 3510 g04 1.5 1.0 C25 0 50 100 125 0.5 0 minimum input voltage shutdown threshold voltage temperature (c) C50 current (a) 14 25 3510 g05 8 4 C25 0 50 2 0 16 12 10 6 75 100 125 v vin1 v vin2 temperature (c) C50 2.0 current ( a) 2.2 2.6 2.8 3.0 4.0 3.4 0 50 75 3510 g07 2.4 3.6 3.8 3.2 C25 25 100 125 ind to v out maximum current vs temperature temperature (c) C50 2.0 current (a) 2.2 2.6 2.8 3.0 4.0 3.4 C10 30 50 3510 g30 2.4 3.6 3.8 3.2 C30 10 70 v out = 5v v out = 0v 90 110
lt3510 5 3510fe typical performance characteristics soft-start to feedback offset voltage vs temperature v c switching threshold voltage vs temperature power good threshold voltage vs temperature power good sink current vs temperature minimum switching times vs temperature switching frequency and channel phase vs temperature switching frequency and channel phase vs temperature synchronization clock frequency range vs temperature channel phase vs temperature with external synchronization temperature (c) C50 voltage (mv) 3 25 3510 g08 0 C2 C25 0 50 C3 C4 4 2 1 C1 75 100 125 temperature (c) C50 voltage (v) 800 900 1000 25 75 3510 g09 700 600 C25 0 50 100 125 500 400 v out = 5v v out = 0v temperature (c) C50 600 voltage (v) 620 660 680 700 800 740 0 50 75 3510 g10 640 760 780 720 C25 25 100 125 rising falling temperature (c) C50 500 current (a) 550 650 700 750 1000 850 0 50 75 3510 g11 600 900 950 800 C25 25 100 125 temperature (c) C50 50 time (ns) 70 110 130 150 250 190 0 50 75 3510 g12 90 210 230 170 C25 25 100 125 minimum on time minimum off time temperature (c) C50 200 frequency (khz) phase (deg) 210 230 240 250 300 270 0 50 75 3510 g13 220 280 290 260 100 110 130 140 150 200 170 120 180 190 160 C25 25 100 125 phase frequency r t /sync = 133k temperature (c) C50 frequency (khz) phase (deg) 1550 1600 1650 25 75 3510 g14 1500 1450 C25 0 50 100 125 1400 1350 190 195 200 185 180 175 170 165 160 155 150 frequency phase r rt /sync = 15.4k temperature (c) C50 C25 0 frequency (khz) 1000 2500 0 50 75 3510 g15 500 2000 1500 25 100 125 maximum synchronization frequency minimum synchronization frequency temperature (c) C50 168 phase (deg) 170 174 176 178 188 182 0 50 75 3510 g16 172 164 186 180 C25 25 100 125 synchronization frequency = 250khz synchronization frequency = 1500khz
lt3510 6 3510fe typical performance characteristics external sync duty cycle range vs external sync frequency frequency and phase vs r t /sync pin resistance switch saturation voltage vs switch current minimum boost voltage vs temperature v out + ind current vs temperature v out + ind current vs v out voltage minimum input voltage vs load current minimum input voltage vs load current minimum input voltage vs load current frequency (khz) 250 duty cycle (%) 60 80 100 1250 3510 g17 40 20 50 70 90 30 10 0 500 750 1000 1500 maximum clock duty cycle minimum clock duty cycle resistance (k) 0 20 40 60 80 100 120 140 frequency (khz) phase (deg) 800 1200 3510 g18 400 100 1600 600 1000 200 1400 170 180 160 150 190 165 175 155 185 frequency phase current (a) 0.5 voltage (mv) 150 200 250 1.1 1.5 3510 g19 100 50 0 0.7 0.9 1.3 1.7 1.9 125c 25c C50c temperature (c) C50 C25 0 voltage (v) 1.0 2.5 0 50 75 3510 g21 0.5 2.0 1.5 25 100 125 temperature (c) C50 50 current (a) 55 65 70 75 100 85 0 50 75 3510 g22 60 90 95 80 C25 25 100 125 voltage (v) 0 current (a) 60 80 100 1.6 3510 g23 40 20 50 70 90 30 10 0 0.4 0.2 0.8 0.6 1.2 1.4 1.8 1.0 2.0 current (ma) 1 2.0 voltage (v) 2.5 3.0 3.5 4.0 4.5 5.0 10 100 1000 10000 3510 g24 v out = 2.5v running current (ma) 1 4.5 voltage (v) 5.0 5.5 6.0 6.5 7.0 7.5 10 100 1000 10000 3510 g26 v out = 5v running current (ma) 1 3.0 voltage (v) 3.5 4.0 4.5 5.0 5.5 6.0 10 100 1000 10000 3510 g25 v out = 3.3v running
lt3510 7 3510fe typical performance characteristics dropout operation inductor value vs frequency for 2a maximum load current inductor value vs frequency for 2a maximum load current input voltage (v) 2 0 output voltage (v) 1 2 3 4 34 5 6 3510 g27 5 6 2.5 3.5 4.5 5.5 frequency 1.5mhz 250khz load = 1a v out = 5v v out = 3.3v input voltage (v) 7 250 frequency (khz) 500 1000 1250 1500 11 15 17 25 3510 g28 750 913 19 21 23 l = 2.2 h l = 3.3 h l = 4.7 h l = 6.8 h v out = 3.3v i ripple = 1a input voltage (v) 10 250 frequency (khz) 500 750 1000 1250 1500 12.5 15 17.5 20 3510 g29 22.5 25 v out = 5v i ripple = 1a l = 2.2 h l = 3.3 h l = 4.7 h l = 6.8 h l = 10 h
lt3510 8 3510fe v in1 (pin 1): the v in1 pin powers the internal control circuitry for both channels and is monitored by the undervoltage lockout comparator. the v in1 pin is also connected to the collector of channel 1s on-chip power npn switch. the v in1 pin has high di/dt edges and must be decoupled to ground close to the pin of the device. sw1/sw2 (pins 2, 9): the sw pin is the emitter of the on- chip power npn. at switch off, the inductor will drive this pin below ground with a high dv/dt. an external schottky catch diode to ground, close to the sw pin and respective v in decoupling capacitors ground, must be used to prevent this pin from excessive negative voltages. ind1/ind2 (pins 3, 8): the ind pin is the input to the on-chip sense resistor that measures current ? owing in the inductor. when the current in the resistor exceeds the current dictated by the v c pin, the sw latch is held in reset, disabling the output switch. bias current ? ows out of the ind pin when ind is less than 1.6v. v out1 /v out2 (pins 4, 7): the v out pin is the output to the on-chip sense resistor that measures current ? owing in the inductor. when the current in the resistor exceeds the current dictated by the v c pin, the sw latch is held in reset, disabling the output switch. bias current ? ows out of the v out pin when v out is less than 1.6v. pg1/pg2 (pins 5, 6): the power good pin is an open-col- lector output that sinks current when the feedback falls below 90% of its nominal regulating voltage. for v in1 above 1v, its output state remains true, although during shutdown, v in1 undervoltage lockout or thermal shutdown, its current sink capability is reduced. the pg pins can be left open circuit or tied together to form a single power good signal. v in2 (pin 10): the v in2 pin is the collector of channel 2s on-chip power npn switch. this pin is independent of v in1 and may be connected to the same or a separate supply. in either case, high di/dt edges are present and decoupling to ground must be used close to this pin. ss1/ss2 (pins 19, 12): the ss1/2 pins control the soft- start and sequence of their respective outputs. a single capacitor from the ss pin to ground determines the outpt ramp rate. for soft-start and output tracking/sequencing details, see the applications information section. v c1 /v c2 (pins 18, 13): the v c pin is the output of the error ampli? er and the input to the peak switch current comparator. it is normally used for frequency compensa- tion, but can also be used as a current clamp or control loop override. if the error ampli? er drives v c above the maximum switch current level, a voltage clamp activates. this indicates that the output is overloaded and current is pulled from the ss pin, reducing the regulation point. fb1/fb2 (pins 17, 14): the fb pin is the negative input to the error ampli? er. the output switches regulate this pin to 0.8v, with respect to the exposed ground pad. bias current ? ows out of the fb pin. shdn (pin 15): the shutdown pin is used to turn off both channels and control circuitry to reduce quiescent current to a typical value of 9a. the accurate 1.28v threshold and input current hysteresis can be used as an undervoltage lockout, preventing the regulator from operating until the input voltage has reached a predetermined level. force the shdn pin above its threshold or let it ? oat for normal operation. r t /sync (pin 16): this r t /sync pin provides two modes of setting the constant switch frequency. connecting a resistor from the r t /sync pin to ground will set the r t /sync pin to a typical value of 0.975v. the resultant switching frequency will be set by the resistor value. the minimum value of 15.4k and maximum value of 133k sets the switching frequency to 1.5mhz and 250khz respectively. driving the r t /sync pin with an external clock signal will synchronize the switch to the applied frequency. synchro- nization occurs on the rising edge of the clock signal after pin functions
lt3510 9 3510fe pin functions the clock signal is detected, with switch 1 in phase with the synchronization signal. each rising clock edge initiates an oscillator ramp reset. a gain control loop servos the oscillator charging current to maintain a constant oscillator amplitude. hence, the slope compensation and channel phase relationship remain unchanged. if the clock signal is removed, the oscillator reverts to resistor mode and reapplies the 0.975v bias to the r t /sync pin after the synchronization detection circuitry times out. the clock source impedance should be set such that the current out of the r t /sync pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. bst1/bst2 (pins 20, 11): the bst pin provides a higher than v in base drive to the power npn to ensure a low switch drop. a comparator to v in imposes a minimum off time on the sw pin if the bst pin voltage drops too low. forcing a sw off time allows the boost capacitor to recharge. exposed pad (pin 21): gnd. the exposed pad gnd pin is the only ground connection for the device. the exposed pad should be soldered to a large copper area to reduce thermal resistance. the gnd pin is common to both chan- nels and also serves as small-signal ground. for ideal operation all small-signal ground paths should connect to the gnd pin at a single point, avoiding any high current ground returns.
lt3510 10 3510fe block diagram figure 1. block diagram (one of two switching regulators shown) the lt3510 is dual channel, constant frequency, current mode buck converter with internal 2a switches. each channel is identical with a common shutdown pin, internal regulator, oscillator, undervoltage detect, thermal shutdown and power-on reset. if the shdn pin is taken below its 1.28v threshold the lt3510 will be placed in a low quiescent current mode. in this mode the lt3510 typically draws 9a from v in1 and <1a from v in2 . in shutdown mode the pg is active with a typical sink capability of 50a for v in1 voltage greater than 2v. when the shdn pin is opened or driven above 1.28v, the internal bias circuits turn on generating an internal regulated voltage, 0.8v fb , 0.975v r t /sync references, and a por signal which sets the soft-start latch. as the r t /sync pin reaches its 0.975v regulation point, the internal oscillator will start generating two clock sig- nals 180 out of phase for each regulator at a frequency determined by the resistor from the r t /sync pin to ground. alternatively, if a synchronization signal is detected by the lt3510 at the r t /sync pin, clock signals 180 out of phase + 3 + C + C + C internal regulator and reference oscillator and agc por undervoltage tsd 7a shutdown comparator r t /sync r3 v in1 shdn 3a 1.28v gnd s 0.8v lowest voltage power good comparator soft-start reset comparator 0.72v v c c rq 3.25a clk1 one channel clk2 r s q pre driver circuitry dropout enhancement slope compensation + C + C + C v in v out bst l1 d d r1 r2 c3 c sw ind fb pgood 3510 bd + + + 80mv c ss v c clamp ss clamp applications information
lt3510 11 3510fe applications information will be generated at the incoming frequency on the rising edge of the synchronization pulse with switch 1 in phase with the synchronization signal. in addition, the internal slope compensation will be automatically adjusted to pre- vent subharmonic oscillation during synchronization. the two regulators are constant frequency, current mode step-down converters. current mode regulators are con- trolled by an internal clock and two feedback loops that control the duty cycle of the power switch. in addition to the normal error ampli? er, there is a current sense ampli? er that monitors switch current on a cycle-by-cycle basis. this technique means that the error ampli? er commands current to be delivered to the output rather than voltage. a voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180, shift will occur. the current fed sys- tem will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the lc resonant frequency. this makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. the block diagram in figure 1 shows only one of the switching regulators whose operation will be discussed below. the additional regulator will operate in a similar manner with the exception that its clock will be 180 out of phase with the other regulator. when, during power up, the por signal sets the soft-start latch, both ss pins will be discharged to ground to ensure proper start-up operation. when the ss pin voltage drops below 80mv, the v c pin is driven low disabling switching and the soft-start latch is reset. once the latch is reset the soft-start capacitor starts to charge with a typical value of 3.25a. as the voltage rises above 80mv on the ss pin, the v c pin will be driven high by the error ampli? er. when the voltage on the v c pin exceeds 0.7v, the clock set pulse sets the driver ? ip-? op which turns on the internal power npn switch. this causes current from v in , through the npn switch, inductor and internal sense resistor, to increase. when the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the v c pin, the ? ip-? op is reset and the internal npn switch is turned off. once the switch is turned off the inductor will drive the voltage at the sw pin low until the external schottky diode starts to conduct, decreasing the current in the inductor. the cycle is repeated with the start of each clock cycle. however, if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the ? ip-? op will not be set resulting in a further decrease in inductor current. since the output current is controlled by the v c voltage, output regulation is achieved by the error ampli? er continually adjusting the v c pin voltage. the error ampli? er is a transconductance ampli? er that compares the fb voltage to the lowest voltage present at either the ss pin or an internal 0.8v reference. compensa- tion of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the v c pin to ground. since the ss pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. if the current demanded by the output exceeds the maxi- mum current dictated by the v c pin clamp, the ss pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. when overload is removed, the output will soft-start from the overload regulation point. v in1 undervoltage detection or thermal shutdown will set the soft-start latch, resulting in a complete soft-start sequence. the switch driver operates from either the v in or bst volt- age. an external diode and capacitor are used to generate a drive voltage higher than v in to saturate the output npn and maintain high ef? ciency. if the bst capacitor voltage is suf? cient, the switch is allowed to operate to 100% duty cycle. if the boost capacitor discharges towards a level insuf? cient to drive the output npn, a bst pin compara- tor forces a minimum cycle off time, allowing the boost capacitor to recharge. a power good comparator with 30mv of hysteresis trips at 90% of regulated output voltage. the pg output is an open-collector npn that is off when the output is in regu- lation allowing a resistor to pull the pg pin to a desired voltage.
lt3510 12 3510fe applications information choosing the output voltage the output voltage is programmed with a resistor divider between the output and the fb pin. choose the 1% resis- tors according to: r1 = r2 ? v out 0.8v ?1 ? ? ? ? ? ? r2 should be 10k or less to avoid bias current errors. refer- ence designators refer to the block diagram in figure 1. choosing the switching frequency the lt3510 switching frequency is set by resistor r3 in figure 1. the r t /sync pin is internally regulated at 0.975v. setting resistor r3 sets the current in the r t /sync pin which determines the oscillator frequency as illustrated in figure 2. the switching frequency is typically set as high as pos- sible to reduce overall solution size. the lt3510 employs techniques to enhance dropout at high frequencies but ef? ciency and maximum input voltage decrease due to switching losses and minimum switch on times. the maximum recommended frequency can be approximated by the equation: frequency (hz) = v out + v d v in ?v sw + v d ? 1 t on(min) where v d is the forward voltage drop of the catch diode (d1 figure 2), v sw is the voltage drop of the internal switch, and t on(min) in the minimum on time of the switch, all at maximum load current. the following example along with the data in table 1 illustrates the tradeoffs of switch frequency selection. example. v in = 25v, v out = 3.3v, i out = 2.5a, temperature = 0c to 85c t on(min) = 200ns (85c from the typical performance characteristics graph), v d = 0.6v, v sw = 0.4v (85c) max frequency = 3.3 + 0.6 25 ? 0.4 + 0.6 ? 1 200e-9 ~ 750khz r t /sync ~ 42k (figure 2) input voltage range once the switching frequency has been determined, the input voltage range of the regulator can be determined. the minimum input voltage is determined by either the lt3510s minimum operating voltage of ~2.8v, or by its figure 2. frequency and phase vs r t /sync resistance table 1. ef? ciency and size comparisons for different r rt/sync values. 3.3v output frequency r t /sync efficiency v vin1/2 = 12v v in(max) ? l* c* l + c area 1.2mhz 20.5k 79.0% 16 1.5h 22f 63mm 2 1.0mhz 26.7k 80.9% 18 2.2h 47f 66mm 2 750khz 38.3k 81.2% 22 3.3h 47f 66mm 2 500khz 61.9k 82.0% 24 4.7h 47f 66mm 2 250khz 133k 83.9% 24 10h 100f 172mm 2 ? v in(max) is de? ned as the highest input voltage that maintains constant output voltage ripple. *inductor and capacitor values chosen for stability and constant ripple current. resistance (k) 0 20 40 60 80 100 120 140 frequency (khz) phase (deg) 800 1200 3510 f02 400 100 1600 600 1000 200 1400 170 180 160 150 190 165 175 155 185 frequency phase
lt3510 13 3510fe maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on during a clock cycle. unlike most ? xed frequency regulators, the lt3510 will not switch off at the end of each clock cycle if there is suf? cient volt- age across the boost capacitor (c3 in figure 1) to fully saturate the output switch. forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. this operation has the same effect as lowering the clock frequency for a ? xed off time, resulting in a higher duty cycle and lower minimum input voltage. the resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: dc max = 1 1 + 1 b where b is 2a divided by the typical boost current from the electrical characteristics. this leads to a minimum input voltage of: v in(min) = v out + v d dc max ?v d + v sw where v sw is the voltage drop of the internal switch. figure 3 shows a typical graph of minimum input voltage vs load current for the 3.3v and 1.8v application on the ? rst page of this data sheet. the maximum input voltage is determined by the absolute maximum ratings of the v in and bst pins and by the frequency and minimum duty cycle. the minimum duty cycle is de? ned as : dc min = t on(min) ? frequency maximum input voltage as: v in(max) = v out + v d dc min ?v d + v sw note that the lt3510 will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the v in and bst pins are not violated. however operation in this region of input voltage will exhibit pulse skipping behavior. example: v out = 3.3v, i out = 1a, frequency = 1mhz, temperature = 25c v sw = 0.1v, b = 40 (from boost characteristics speci? ca- tion), v d = 0.4v, t on(min) = 200ns dc max = 1 1 + 1 40 = 98% v in(min) = 3.3 + 0.4 0.98 ? 0.4 + 0.1 = 3.48v dc min = t min(on) ?f = 0.200 v in(max) = 3.3 + 0.4 0.200 ? 0.4 + 0.1 = 18.2v inductor selection and maximum output current a good ? rst choice for the inductor value is: l = v in ?v out () ?v out v in ?f where f is frequency in mhz and l is in h. with this value the maximum load current will be ~2a, independent of input voltage. the inductors rms current figure 3. minimum input voltage vs load current current (ma) 1 3.0 voltage (v) 3.5 4.0 4.5 5.0 5.5 6.0 10 100 1000 10000 3510 f03 v out = 3.3v start-up running applications information
lt3510 14 3510fe rating must be greater than your maximum load current and its saturation current should be about 30% higher. to keep ef? ciency high, the series resistance (dcr) should be less than 0.05 . for applications with a duty cycle of about 50%, the induc- tor value should be chosen to obtain an inductor ripple current less than 40% of peak switch current. of course, such a simple design guide will not always result in the optimum inductor for your application. a larger value provides a slightly higher maximum load current, and will reduce the output voltage ripple. if your load is lower than 2a, then you can decrease the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher ef? ciency. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to- peak inductor ripple current. the lt3510 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt3510 will deliver depends on the current limit, the inductor value, switch frequency, and the input and output voltages. the inductor is chosen based on output current requirements, output voltage ripple requirements, size restrictions and ef? ciency goals. when the switch is off, the inductor sees the output volt- age plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: i l = 1? dc () v out + v d () l?f where f is the switching frequency of the lt3510 and l is the value of the inductor. the peak inductor and switch current is: i sw pk () = i lpk = i out + i l 2 to maintain output regulation, this peak current must be less than the lt3510s switch current limit i lim . i lim is 2.5a over the entire duty cycle range. the maximum output current is a function of the chosen inductor value: i out(max) = i lim ? i l 2 = 2.5 ? i l 2 if the inductor value is chosen so that the ripple current is small, then the available output current will be near the switch current limit. one approach to choosing the inductor is to start with the simple rule given above, look at the available inductors and choose one to meet cost or space goals. then use these equations to check that the lt3510 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. discontinuous operation occurs when i out is less than i l /2 as calculated above. figure 4 illustrates the inductance value needed for a 3.3v output with a maximum load capability of 2a. referring to figure 4, an inductor value between 3.3h and 4.7h will be suf? cient for a 15v input voltage and a switch frequency of 750khz. there are several graphs in the typical performance characteristics section of this data sheet that show inductor selection as a function of input voltage and switch frequency for several popular output figure 4. inductor values for 2a maximum load current vs frequency and input voltage input voltage (v) 10 250 frequency (khz) 500 750 1000 1250 1500 12.5 15 17.5 20 3510 f04 22.5 25 v out = 5v i ripple = 1a l = 2.2h l = 3.3h l = 4.7h l = 6.8h l = 10h applications information
lt3510 15 3510fe voltages and output ripple currents. also, low inductance may result in discontinuous mode operation, which is okay, but further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technology application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), there is a minimum inductance required to avoid subharmonic oscillations. see application note 19 for more information. input capacitor selection bypass the inputs of the lt3510 circuit with a 4.7f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capaci- tor is required to reduce the resulting voltage ripple at the lt3510 and to force this very high frequency switching current into a tight local loop, minimizing emi. the input capacitor must have low impedance at the switching fre- quency to do this effectively, and it must have an adequate ripple current rating. with two switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor rms current is not simple. however, a conservative value is the rms input current for the channel that is delivering most power (v out ? i out ). this is given by: i cin(rms) = i out v out ?v in ?v out () v in < i out 2 and is largest when v in = 2v out (50% duty cycle). as the second, lower power channel draws input current, the input capacitors rms current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. considering that the maximum load current from a single channel is ~2a, rms ripple current will always be less than 1a. the frequency, v in to v out ratio, and maximum load cur- rent requirement of the lt3510 along with the input supply source impedance, determine the energy storage require- ments of the input capacitor. determine the worst-case condition for input ripple current and then size the input capacitor such that it reduces input voltage ripple to an acceptable level. typical values for input capacitors run from 10f at low frequencies to 2.2f at higher frequencies. the combination of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors make them the preferred choice. the low esr results in very low voltage ripple and the capacitors can handle plenty of ripple current. they are also comparatively robust and can be used in this application at their rated voltage. x5r and x7r types are stable over temperature and applied voltage, and give dependable service. other types (y5v and z5u) have very large temperature and voltage coef? cients of capacitance, so they may have only a small fraction of their nominal capacitance in your application. while they will still handle the rms ripple current, the input voltage ripple may become fairly large, and the ripple current may end up ? owing from your input supply or from other by- pass capacitors in your system, as opposed to being fully sourced from the local input capacitor. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10f will be required to meet the esr and ripple current require- ments. because the input capacitor is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. the manufacturer may also recommend operation below the rated voltage of the capacitor. be sure to place the 1f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. when the lt3510s input supplies are operated at different input voltages, an input capacitor sized for that channel should be placed as close as possible to the respective v in pins. a ? nal caution regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plugging the circuit into a live power source) this tank can ring, doubling the applications information
lt3510 16 3510fe input voltage and damaging the lt3510. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details, see application note 88. output capacitor selection typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switch- ing frequency. this means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. with an allowable 5% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: c vout = max load step frequency ? 0.05 ? v out example: v out = 3.3v, frequency = 1mhz, max load step = 2a c vout = 2 1e6 ? 0.05 ? 3.3v = 12 f the calculated value is only a suggested starting value. increase the value if transient response needs improvement or reduce the capacitance if size is a priority. the output capacitor ? lters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and to stabilize the lt3510s control loop. the switching frequency of the lt3510 deter- mines the value of output capacitance required. also, the current mode control loop doesnt require the presence of output capacitor series resistance (esr). for these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. estimate output ripple with the following equations: v ripple = ? i l /(8f c out ) for ceramic capacitors, and v ripple = ? i l esr for electrolytic capacitors (tantalum and aluminum) where ? i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low, and the rms current rating of the output capacitor is usually not of concern. another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. for a 5% overshoot, this require- ment becomes: c out > 10 l i lim v out ? ? ? ? ? ? 2 finally, there must be enough capacitance for good transient performance. the last equation gives a good starting point. alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. this topic is covered more thoroughly in the section on loop compensation. the high performance (low esr), small size and robustness of ceramic capacitors make them the preferred type for lt3510 applications. however, all ceramic capacitors are not the same. as mentioned above, many of the high value capacitors use poor dielectrics with high temperature and voltage coef? cients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and temperature extremes. because the loop stability and transient response depend on the value of c out , you may not be able to tolerate this loss. use x7r and x5r types. you can also use electrolytic capacitors. the esrs of most aluminum electrolytics are too large to deliver low output ripple. tantalum and newer, lower esr organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the esr. the choice of capacitor value will be based on the esr required for low ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple per- formance. one bene? t is that the larger capacitance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. applications information
lt3510 17 3510fe table 2 vendor type series taiyo yuden ceramic x5r, x7r avx ceramic x5r, x7r tantalum kemet tantalum ta organic al organic t491, t494, t495 t520 a700 sanyo ta/al organic poscap panasonic al organic sp cap tdk ceramic x5r, x7r catch diode the diode d1 conducts current only during switch off time. use a schottky diode to limit forward voltage drop to increase ef? ciency. the schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. average forward current can be calculated from: i d(avg) = i out v in ?v in ?v out () the only reason to consider a larger diode is the worst- case condition of a high input voltage and shorted output. with a shorted condition, diode current will increase to a typical value of 3a, determined by the peak switch current limit of the lt3510. this is safe for short periods of time, but it would be prudent to check with the diode manu- facturer if continuous operation under these conditions can be tolerated. bst pin considerations the capacitor and diode tied to the bst pin generate a voltage that is higher than the input voltage. in most cases a 0.47f capacitor and fast switching diode (such as the cmdsh-3 or fmmd914) will work well. almost any type of ? lm or ceramic capacitor is suitable, but the esr should be <1 to ensure it can be fully recharged during the off time of the switch. the capacitor value can be approximated by: c bst = i out(max) ?dc b? v out ?v bst(min) () ?f where i out(max) is the maximum load current, and v bst(min) is the minimum boost voltage to fully saturate the switch. figure 5 shows four ways to arrange the boost circuit. the bst pin must be more than 1.4v above the sw pin for full ef? ciency. generally, for outputs of 3.3v and higher the standard circuit (figure 5a) is the best. for outputs between 2.8v and 3.3v, replace the d2 with a small schottky diode such as the pmeg4005. for lower output voltages the boost diode can be tied to the input (figure 5b). the circuit in figure 5a is more ef? cient because the bst pin current comes from a lower voltage source. figure 5c shows the boost voltage source from available dc sources that are greater than 3v. the highest ef? ciency is attained by choosing the lowest boost voltage above 3v. for example, if you are generating 3.3v and 1.8v and the 3.3v is on whenever the 1.8v is on, the 1.8v boost diode can be connected to the 3.3v output. in any case, you must also be sure that the maximum voltage at the bst pin is less than the maximum speci? ed in the absolute maximum ratings section. the boost circuit can also run directly from a dc voltage that is higher than the input voltage by more than 3v, as in figure 5d. the diode is used to prevent damage to the lt3510 in case v x is held low while v in is present. the circuit saves several components (both bst pins can be tied to d2). however, ef? ciency may be lower and dissipa- tion in the lt3510 may be higher. also, if v x is absent, the lt3510 will still attempt to regulate the output, but will do so with very low ef? ciency and high dissipation because the switch will not be able to saturate, dropping 1.5v to 2v in conduction. the minimum input voltage of an lt3510 application is limited by the minimum operating voltage (<3v) and by the maximum duty cycle as outlined above. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt3510 is turned on with its ss pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on applications information
lt3510 18 3510fe input and output voltages, and on the arrangement of the boost circuit. the typical performance characteristics section shows plots of the minimum load current to start and to run as a function of input voltage for 3.3v and 5v outputs. in many cases the discharged output capacitor will present a load to the switcher which will allow it to start. the plots show the worst-case situation where v in is ramping very slowly. use a schottky diode for the lowest start-up voltage. frequency compensation the lt3510 uses current mode control to regulate the output. this simpli? es loop compensation. in particular, the lt3510 does not require the esr of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. frequency compensation is provided by the components tied to the v c pin. generally a capacitor and a resistor in series to ground determine loop gain. in addition, there is a lower value capacitor in parallel. this capacitor is not part of the loop compensation but is used to ? lter noise at the switching frequency. loop compensation determines the stability and transient performance. designing the compensation network is a bit complicated and the best values depend on the application and in particular the type of output capacitor. a practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the com- pensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discus- sion of loop compensation and describes how to test the stability using a transient load. figure 6 shows an equivalent circuit for the lt3510 control loop. the error amp is a transconductance ampli? er with ? nite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance ampli? er generating an output cur- rent proportional to the voltage at the v c pin. note that figure 5. bst pin considerations v in v in v x > v in + 3v bst d2 gnd lt3510 sw ind v out v bst C v sw = v x v bst(max) = v x v x(min) = v in + 3v v out < 3v 3510 f05 v in v in v x = lowest v in or v out > 3v bst d2 gnd lt3510 sw ind v out v bst C v sw = v x v bst(max) = v in + v x v x(min) = 3v v out < 3v c3 v in v in bst d2 gnd ( 5d ) ( 5c ) (5b) lt3510 sw ind v out v bst C v sw = v in v bst(max) = 2 ??v in v out < 3v c3 v in v in bst d2 gnd (5a) lt3510 sw ind v out v bst C v sw = v out v bst(max) = v in + v out v out c3 applications information
lt3510 19 3510fe the output capacitor integrates this current, and that the capacitor on the v c pin (c c ) integrates the error ampli- ? er output current, resulting in two poles in the loop. in most cases a zero is required and comes from either the output capacitor esr or from a resistor in series with c c . this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. a phase lead capacitor (c pl ) across the feedback divider may improve the transient response. synchronization the r t /sync pin can be used to synchronize the regulators to an external clock source. driving the r t /sync resistor with a clock source triggers the synchronization detection circuitry. once synchronization is detected, the rising edge of sw1 will be synchronized to the rising edge of the r t /sync pin signal. an agc loop will adjust the internal oscillators to maintain a 180 degree phase between sw1 and sw2, and also adjust slope compensation to avoid subharmonic oscillation. the synchronizing clock signal input to the lt3510 must have a frequency between 250khz and 1.5mhz, a duty cycle between 20% and 80%, a low state below 0.5v and a high state above 1.6v. synchronization signals outside of these parameters will cause erratic switching behavior. the r t /sync resistor should be set such that the free running frequency ((v rt/sync C v synclo )/r rt/sync ) is approximately equal to the synchronization frequency. if the synchronization signal is halted, the synchronization detection circuitry will timeout in typically 10s at which time the lt3510 reverts to the free-running frequency based on the current through r t /sync. if the r t /sync resistor is held above 2v at any time, switching will be disabled. if the synchronization signal is not present during regula- tor start-up (for example, the synchronization circuitry is powered from the regulator output) the r t /sync pin must see an equivalent resistance to ground between 15.4k and 133k until the synchronization circuitry is active for proper start-up operation. if the synchronization signal powers up in an undetermined state (v ol , v oh , hi-z), connect the synchronization clock to the lt3510 as shown in figure 7. the circuit as shown will isolate the synchronization signal when the output voltage is below 90% of the regulated output. the lt3510 will start-up with a switching frequency determined by the resistor from the r t /sync pin to ground. if the synchronization signal powers up in a low impedance state (v ol ), connect a resistor between the r t /sync pin and the synchronizing clock. the equivalent resistance seen from the r t /sync pin to ground will set the start-up frequency. figure 6. model for loop response figure 7. synchronous signal powered from regulators output + + C 0.8v sw lt3510 fb v c c f c pl output c1 c1 3510 f06 c c r c r1 esr tantalum or polymer ceramic r2 error amp g m = 275 mho current mode power stage g m = 2.2mho 3.6m lt3510 synchronization circuitry v out1 r t /sync 3510 f07 v cc clk pg1 applications information
lt3510 20 3510fe figure 8. undervoltage lockout if the synchronization signal powers up in a high impedance state (hi-z), connect a resistor from the r t /sync pin to ground. the equivalent resistance seen from the r t /sync pin to ground will set the start-up frequency. if the synchronization signal changes between high and low impedance states during power up (v ol , hi-z), connect the synchronization circuitry to the lt3510 as shown in the typical applications section. this will allow the lt3510 to start-up with a switching frequency determined by the equivalent resistance from the r t /sync pin to ground. shutdown and undervoltage lockout figure 8 shows how to add undervoltage lockout (uvlo) to the lt3510. typically, uvlo is used in situations where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. an internal comparator will force the part into shutdown below the minimum v in1 of 2.8v. this feature can be used to prevent excessive discharge of battery-operated systems. since v in2 supplies the output stage of channel 2 and is not monitored, care must be taken to insure that v in2 is present before channel 2 is allowed to switch. if an adjustable uvlo threshold is required, the shdn pin can be used. the threshold voltage of the shdn pin comparator is 1.28v. a 3a internal current source defaults the open-pin condition to be operating (see typical performance characteristics). current hysteresis is added above the shdn threshold. this can be used to set voltage hysteresis of the uvlo using the following: r1 = v h ?v l 7 a r2 = 1.28 v h ?1.28 r1 + 3 a v h = turn-on threshold v l = turn-off threshold example: switching should not start until the input is above 4.75v and is to stop if the input falls below 3.75v. v h = 4.75v v l = 3.75v r1 = 4.75 ? 3.75 7 a ? 143k r2 = 1.28 4.75 ? 1.28 143k + 3 a ? 47k keep the connections from the resistors to the shdn pin short and make sure that the interplane or surface capacitance to switching nodes is minimized. if high re- sistor values are used, the shdn pin should be bypassed with a 1nf capacitor to prevent coupling problems from the switch node. soft-start the output of the lt3510 regulates to the lowest voltage present at either the ss pin or an internal 0.8v reference. a capacitor from the ss pin to ground is charged by an internal 3.25a current source resulting in a linear output ramp from 0v to the regulated output whose duration is given by: t ramp = c ss ? 0.8v 3.25 a + + C 1.28v 7a 3a r1 r2 c1 shdn internal regulator v in1 v in1 > 2.8v 3510 f08 v in1 or v in2 lt3510 applications information
lt3510 21 3510fe at power-up, a reset signal sets the soft-start latch and discharges both ss pins to approximately 0v to ensure proper start-up. when both ss pins are fully discharged the latch is reset and the internal 3.25a current source starts to charge the ss pin. when the ss pin voltage is below 50mv, the v c pin is pulled low which disables switching. this allows the ss pin to be used as an individual shutdown for each channel. as the ss pin voltage rises above 50mv, the v c pin is re- leased and the output is regulated to the ss voltage. when the ss pin voltage exceeds the internal 0.8v reference, the output is regulated to the reference. the ss pin voltage will continue to rise until it is clamped at 2v. in the event of a v in1 undervoltage lockout, the shdn pin driven below 1.28v, or the internal die temperature exceeding its maximum rating during normal operation, the soft-start latch is set, triggering a start-up sequence. in addition, if the load exceeds the maximum output switch current, the output will start to drop causing the v c pin clamp to be activated. as long as the v c pin is clamped, the ss pin will be discharged. as a result, the output will be regulated to the highest voltage that the maximum output current can support. for example, if a 6v output is loaded by 1 the ss pin will drop to 0.4v, regulating the output at 3v ( 3a ? 1 ). once the overload condition is removed, the output will soft-start from the temporary voltage level to the normal regulation point. since the ss pin is clamped at 2v and has to discharge to 0.8v before taking control of regulation, momentary overload conditions will be tolerated without a soft-start recovery. the typical time before the ss pin takes control is: t ss(control) = c ss ?1.2v 700 a power good indicators the pg pin is the open-collector output of an internal comparator. the comparator compares the fb pin voltage to 90% of the reference voltage with 30mv of hysteresis. the pg pin has a sink capability of 800a when the fb pin is below the threshold and can withstand 25v when the threshold is exceeded. the pg pin is active (sink capability is reduced in shutdown and undervoltage lockout mode) as long as the v in1 pin voltage exceeds 1v. output tracking/sequencing complex output tracking and sequencing between chan- nels can be implemented using the lt3510s ss and pg pins. figure 9 shows several con? gurations for output tracking/sequencing for a 3.3v and 1.8v application. independent soft-start for each channel is shown in figure 9a. the output ramp time for each channel is set by the soft-start capacitor as described in the soft-start section. ratiometric tracking is achieved in figure 9b by connecting both ss pins together. in this con? guration, the ss pin source current is doubled (6.5a) which must be taken into account when calculating the output rise time. by connecting a feedback network from v out1 to the ss2 pin with the same ratio that sets v out2 voltage, absolute tracking shown in figure 9c is implemented. the minimum value of the top feedback resistor (r1) should be set such that the ss pin can be driven all the way to ground with 700a of sink current when v out1 is at its regulated voltage. in addition, a small v out2 voltage offset will be present due to the ss2 3.25a source current. this offset can be corrected for by slightly reducing the value of r2. figure 9d illustrates output sequencing. when v out1 is within 10% of its regulated voltage, pg1 releases the ss2 soft-start pin allowing v out2 to soft-start. in this case pg1 will be pulled up to 2v by the ss pin. if a greater voltage is needed for pg1 logic, a pull-up resistor to v out1 can be used. this will decrease the soft-start ramp time and increase tolerance to momentary shorts. if precise output ramp up and down is required, drive the ss pins as shown in figure 9e. the minimum value of resistor (r3) should be set such that the ss pin can be driven all the way to ground with 700a of sink current during power-up and fault conditions. multiple input voltages for applications requiring large inductors due to high v in to v out ratios, a 2-stage step-down approach may reduce applications information
lt3510 22 3510fe figure 9 ss1 (9a) lt3510 v out1 pg1 pg2 v out2 ss2 0.1f 0.22f 1.8v 3.3v v out1 0.5v/div v out2 0.5v/div 5ms/div v out1 0.5v/div v out2 0.5v/div v out1 0.5v/div v out2 0.5v/div 10ms/div 10ms/div ss1 (9b) lt3510 v out1 pg1 v out2 ss2 0.1f 1.8v 3.3v ss1 (9e) lt3510 v out1 pg1 v out2 ss2 1.8v 3.3v independent start-up ratiometric start-up absolute start-up ss1 (9d) lt3510 v out1 pg1 v out2 ss2 0.1f 0.1f 1.8v 3.3v r3 25k external source output sequencing controlled power up and down + C ss1 (9c) lt3510 v out1 pg1 v out2 ss2 0.22f 1.8v 3.3v r1 13.7k r2 8.08k pg2 pg2 pg1 v out1 0.5v/div v out2 0.5v/div v out1 0.5v/div v out2 0.5v/div 10ms/div 10ms/div pg1 pg1 pg2 pg2 pg1 pg1 ss1/2 pg2 pg2 pg2 pg2 3510 f09 applications information
lt3510 23 3510fe inductor size by allowing an increase in frequency. a dual step down application (figure 10) steps down the input voltage (v in1 ) to the highest output voltage then uses that voltage to power the second output (v in2 ). v out1 must be able to provide enough current for its output plus v out2 maximum load. note that the v out1 must be above v in2 minimum input voltage (2v) when the second channel starts to switch. delaying channel 2 can be accomplished by either independent soft-start capacitors or sequencing with the pg1 output. for example, assume a maximum input of 24v: v in = 24v, v out1 = 5v at 1.5a and v out2 = 1.2v at 1.5a frequency (hz) v out + v d v in ?v sw + v d t min(on) l v in ?v out () ?v out v in ?f figure 10. 5v and 1.2v 2-stage step-down converter with output sequencing single step down: frequency (hz) 1.2 + 0.6 24 ? 0.4 + 0.6 190ns = 392khz l1 = 24 ? 5 () ?5 24 ? 392khz 10 h l2 = 24 ? 1.2 () ? 1.2 24 ? 392khz 2.7 h 2-stage step-down: frequency 5 + 0.6 24 ? 0.4 + 0.6 190ns = 1.2mhz max frequency = 1.2mhz l1 = 24 ? 5 () ?5 24 ? 1.2mhz 3.3 h l2 = 5 ? 1.2 () ? 1.2 5 ? 1.2mhz 0.76 h shdn 4.7 f 47 f 42.3k 100k 26.7k pmeg4005 8.06k pmeg4005 10pf 470pf 3.3 h 1 h v out1 5v v out2 1.2v v in 6v to 24v 0.47 f 47 f s 2 0.47 f 10pf b360a b360a v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 fset bst2 sw2 ind2 v out2 pg2 fb2 v c2 ss/track2 40.2k 4k 8.06k 3510 f10 32.4k 0.1 f 0.1 f 470pf applications information
lt3510 24 3510fe figure 11. subtracting the current when the switch is on (11a) from the current when the switch is off (11b) reveals the path o f the high frequency switching current (11c). keep this loop small. the voltage on the sw and bst traces will also be switched; keep these traces as short as possible. finally, make sure the circuit is shielded with a local ground plane pcb layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 11 shows the high di/dt paths in the buck regulator circuit. note that large switched currents ? ow in the power switch, the catch diode and the input capacitor. the loop formed by these components should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board and their connections should be made on that layer. place a local, unbroken ground plane below these com- ponents, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c2. additionally, the sw and bst traces should be kept as short as possible. the topside metal from the dc964a demonstration board in figure 12 illustrates proper component placement and trace routing. thermal considerations the pcb must also provide heat sinking to keep the lt3510 cool. the exposed metal on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the lt3510. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper figure 12. topside pcb layout v in gnd (11a) lt3510 sw v in gnd (11c) lt3510 sw v in gnd (11b) lt3510 sw 3510 f11 applications information
lt3510 25 3510fe to the internal planes with vias can further reduce ther- mal resistance. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 45c/w. the power dissipation in the other power components such as catch diodes, boost diodes and inductors, cause additional copper heating and can further increase what the ic sees as ambient temperature. see the lt1767 data sheets thermal considerations section. single, low ripple 4a output the lt3510 can generate a single, low ripple 4a output if the outputs of the two switching regulators are tied together and share a single output capacitor. by tying the two fb pins together and the two v c pins together, the two channels will share the load current. there are several advantages to this 2-phase buck regulator. ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive capacitors. although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. this may be important when there are tight height restrictions on the circuit. there is one special consideration regarding the 2-phase circuit. when the difference between the input voltage and output voltage is less than 2.5v, then the boost circuits may prevent the two channels from properly sharing current. if, for example, channel 1 gets started ? rst, it can supply the load current, while channel 2 never switches enough current to get its boost capacitor charged. in this case, channel 1 will supply the load until it reaches current limit, the output voltage drops, and channel 2 gets started. two solutions to this problem are shown in the typical applications section. the single 3.3v/4a output converter generates a boost sup- ply from either sw that will service both switch pins. the synchronized 3.3v/8a output converter utilizes undervoltage lockout to prevent the start-up condition. other linear technology publications application notes an19, an35 and an44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note dn100 shows how to generate a dual (+ and C) output supply using a buck regulator. applications information
lt3510 26 3510fe 5v and 2.5v with absolute tracking 1.25mhz single 3.3v/4a low ripple output shdn 4.7 f 47 f 42.3k 100k 100k 26.7k 8.06k 470pf 10pf 40.2k 10pf 40.2k 3.3 h 2.2 h v out1 5v v out2 2.5v v in 12v 0.47 f b360a b360a 47 f 0.47 f pmeg4005 pmeg4005 v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 r t /sync bst2 sw2 ind2 v out2 pg2 fb2 v c2 ss/track2 16.9k 8.06k 3510 ta02 0.1 f 7.68k 16.9k 470pf shdn 4.7f 47f s 2 20.5k 8.06k 1000pf 22pf 1.5h 1.5h v out1 3.3v 4a v in 6v to 25v 0.47f 0.47f b360a b360a pmeg4005 pmeg4005 v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 r t /sync bst2 sw2 ind2 v out2 pg2 fb2 v c2 ss/track2 100k 17.8k 24.9k 3510 ta03 0.1f typical applications
lt3510 27 3510fe dual lt3510 synchronized 3.3v/8a output, 3mhz effective switch frequency shdn 10f 47f s 4 24.9k 8.06k 3300pf 47pf 5.3k 3.3h 3.3h v out1 3.3v v in 5.5v to 24v 0.47f b360a 3.3h 0.47f b360a b360a 0.47f pmeg4005 pmeg4005 pmeg4005 pmeg4005 v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 r t /sync bst2 sw2 ind2 v out2 pg2 fb2 v c2 ss/track2 36.5k 49.9k 49.9k 133k 49.9k 49.9k 0.1 m f shdn v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 r t /sync bst2 sw2 ind2 v out2 pg2 fb2 v c2 3510 ta05 ss/track2 3.3h b360a 0.47f v+ ltc6908-1 set mod gnd out1 out2 143k typical applications 1.25mhz single 3.3v/4a low ripple output shdn 47f s 2 20.5k 8.06k 1000pf 22pf 1.5h 1.5h v out1 3.3v 4a v in 4.5v to 6v 0.47f 0.47f b360a pmeg4005 pmeg4005 v in1 v in2 lt3510 gnd bst1 sw1 ind1 v out1 pg1 fb1 v c1 ss/track1 r t /sync bst2 sw2 ind2 v out2 pg2 fb2 v c2 ss/track2 100k 17.8k 24.9k 3510 ta04 0.1f 4.7f 1f* b360a pmeg4005* *additional components added to share the boost voltage when v in <6v. this is required to ensure load sharing between the two channels. pmeg4005*
lt3510 28 3510fe package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe20 (cb) tssop rev i 0211 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation cb
lt3510 29 3510fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number e 6/12 solder pad clari? cation 28 (revision history begins at rev e)
lt3510 30 3510fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0612 rev e ? printed in usa part number description comments lt1766 60v, 1.2a (i out ), 200khz high ef? ciency step-down dc/dc converter v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, i sd = 25a, 16-lead tssope package LT1933 500ma (i out ), 500khz step-down switching regulator in sot-23 v in : 3.6v to 36v, v out(min) = 1.2v, i q = 1.6ma, i sd <1a, thinsot? package lt1936 36v, 1.4a (i out ), 500khz high ef? ciency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 1.2v, i q = 1.9ma, i sd <1a, 8-lead ms8e package lt1940 dual 25v, 1.4a (i out ), 1.1mhz high ef? ciency step-down dc/dc converter v in : 3.6v to 25v, v out(min) = 1.20v, i q = 3.8ma, i sd <30a, 16-lead tssope package lt1976/lt1977 60v, 1.2a (i out ), 200khz/500khz high ef? ciency step-down dc/dc converters with burst mode ? operation v in : 3.3v to 60v, v out(min) = 1.20v, i q = 100a, i sd <1a, 16-lead tssope package lt c ? 3407/ltc3407-2 dual 600ma/800ma, 1.5mhz/2.25mhz synchronous step-down dc/dc converters v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, 3mm 3mm dfn and 10-lead mse packages lt3434/lt3435 60v, 2.4a (i out ), 200khz/500khz high ef? ciency step-down dc/dc converters with burst mode operation v in : 3.3v to 60v, v out(min) = 1.20v, i q = 100a, i sd <1a, 16-lead tssope package lt3437 60v, 400ma (i out ), micropower step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out(min) = 1.25v, i q = 100a, i sd <1a, dfn package lt3493 36v, 1.4a (i out ), 750khz high ef? ciency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 1.9ma, i sd <1a, dfn package lt3501 dual 25v, 2a (i out ), 1.5mhz high ef? ciency step-down dc/dc converter v in : 3.3v to 25v, v out(min) = 0.8v, i q = 3.5ma, i sd <1a, 20-lead tssope package lt3505 36v, 1.2a (i out ), 3mhz high ef? ciency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.78v, i q = 2ma, i sd <2a, 3mm 3mm dfn and 8-lead mse packages lt3506/lt3506a dual 25v, 1.6a (i out ), 575khz/1.1mhz high ef? ciency step-down dc/dc converters v in : 3.6v to 25v, v out(min) = 0.8v, i q = 3.8ma, i sd <30a, 4mm 5mm dfn package ltc3548 dual 400ma/800ma, 2.25mhz synchronous step-down dc/dc converters v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, 3mm 3mm dfn and 10-lead mse packages related parts

▲Up To Search▲

Price & Availability of LT1933

	To Download LT1933 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .